US 12,191,313 B2
Semiconductor device and method for manufacturing the same
Shunpei Yamazaki, Setagaya (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on May 2, 2023, as Appl. No. 18/142,206.
Application 15/235,642 is a division of application No. 13/746,793, filed on Jan. 22, 2013, granted, now 9,419,146, issued on Aug. 16, 2016.
Application 18/142,206 is a continuation of application No. 17/371,450, filed on Jul. 9, 2021, granted, now 11,682,677.
Application 17/371,450 is a continuation of application No. 16/676,641, filed on Nov. 7, 2019, granted, now 11,081,502, issued on Aug. 3, 2021.
Application 16/676,641 is a continuation of application No. 15/235,642, filed on Aug. 12, 2016, abandoned.
Claims priority of application No. 2012-013730 (JP), filed on Jan. 26, 2012; and application No. 2012-014507 (JP), filed on Jan. 26, 2012.
Prior Publication US 2023/0268349 A1, Aug. 24, 2023
Int. Cl. H01L 27/12 (2006.01); H01L 21/02 (2006.01); H01L 27/146 (2006.01); H01L 29/04 (2006.01); H01L 29/08 (2006.01); H01L 29/24 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H10B 41/70 (2023.01)
CPC H01L 27/1229 (2013.01) [H01L 21/02565 (2013.01); H01L 21/02672 (2013.01); H01L 27/1225 (2013.01); H01L 27/14632 (2013.01); H01L 27/14687 (2013.01); H01L 29/04 (2013.01); H01L 29/0847 (2013.01); H01L 29/24 (2013.01); H01L 29/41733 (2013.01); H01L 29/66742 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78693 (2013.01); H10B 41/70 (2023.02)] 15 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a silicon layer comprising a first channel formation region of a first transistor;
a first insulating film over the silicon layer;
a first conductive layer over the first insulating film;
a second insulating film in contact with a side surface of the first conductive layer;
a third insulating film in contact with an upper surface of the second insulating film;
a second conductive layer in contact with an upper surface of the third insulating film;
a third conductive layer in contact with the upper surface of the third insulating film;
an oxide semiconductor layer in contact with the second conductive layer and the third conductive layer, the oxide semiconductor layer comprising a second channel formation region of a second transistor;
a fourth insulating film over the second channel formation region;
a fourth conductive layer over the fourth insulating film;
a fifth insulating film in contact with an upper surface of the fourth conductive layer; and
a fifth conductive layer in contact with an upper surface of the fifth insulating film, the fifth conductive layer overlapping with the third conductive layer,
wherein the second conductive layer is configured to serve as one of a source electrode and a drain electrode of the second transistor,
wherein the third conductive layer is configured to serve as the other of the source electrode and the drain electrode of the second transistor,
wherein an upper surface of the first conductive layer is in contact with the third conductive layer,
wherein the fifth conductive layer overlaps with the first channel formation region, and
wherein the fifth conductive layer comprises a region extending in a direction intersecting with a channel length direction of the second transistor.