US 12,191,311 B2
Semiconductor device including ferroelectric material, neuromorphic circuit including the semiconductor device, and neuromorphic computing apparatus including the neuromorphic circuit
Sangwook Kim, Seongnam-si (KR); Jinseong Heo, Seoul (KR); Yunseong Lee, Osan-si (KR); and Sanghyun Jo, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Dec. 5, 2023, as Appl. No. 18/529,505.
Application 18/529,505 is a continuation of application No. 16/943,161, filed on Jul. 30, 2020, granted, now 11,887,989.
Claims priority of application No. 10-2019-0093357 (KR), filed on Jul. 31, 2019.
Prior Publication US 2024/0113127 A1, Apr. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/786 (2006.01); G06N 3/063 (2023.01); G06N 3/08 (2023.01); H01L 27/12 (2006.01)
CPC H01L 27/1207 (2013.01) [G06N 3/063 (2013.01); G06N 3/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A neuromorphic circuit comprising:
pre-synaptic neuron circuits;
pre-synaptic lines extending in a first direction from the pre-synaptic neuron circuits;
post synaptic neuron circuits;
post synaptic lines extending from the post synaptic neuron circuits in a second direction crossing the first direction; and
synaptic circuits provided at intersections of the pre-synaptic lines and the post synaptic lines,
the synaptic circuits each including a first transistor including a first channel layer of a first conductivity type, a second transistor having a second channel layer of a second conductivity type, and a third transistor being positioned on at least one of the first transistor and the second transistor on a substrate,
wherein the third transistor includes a third channel layer and a gate electrode that are spaced apart from each other in a thickness direction with a gate insulating film therebetween, the third channel layer including at least one of InGaZnO, InZnO, and InSnZnO, and the gate insulating film including a ferroelectric material comprising at least one of HfO, HfxZr1-xO, and ZrO.
 
13. A neuromorphic circuit comprising:
a synaptic circuit including a semiconductor device;
a pre-synaptic neuron circuit;
a pre-synaptic line connecting the synaptic circuit to the pre-synaptic neuron circuit;
a post-synaptic neuron circuit; and
a post-synaptic line connecting the synaptic circuit to the post-synaptic neuron circuit, wherein
the semiconductor device includes a CMOS circuit including a first transistor of a first conductivity type and a second transistor of a second conductivity type, a third transistor, and a contact electrode,
the third transistor includes a gate electrode, a channel, and a gate insulating film,
the gate insulating film includes a ferroelectric material,
the contact electrode is connected to the gate electrode of the third transistor, a drain of the first transistor, and a drain of the second transistor,
the channel of the third transistor is laterally between a source electrode of the third transistor and a drain electrode of the third transistor such that the channel of the third transistor contacts a sidewall of the source electrode of the third transistor and a sidewall of the drain electrode of the third transistor,
the gate electrode is spaced apart vertically from the channel, does not vertically overlap the source electrode of the third transistor, and does not vertically overlap the drain electrode of the third transistor,
the ferroelectric material includes at least one of HfO, HfxZr1-xO, and ZrO,
the ferroelectric material is doped with at least one of Si, Al, Zr, Y, La, Gd, Sr, and Hf, and
the channel of the third transistor includes at least one of InGaZnO, InZnO, and InSnZnO.