US 12,191,308 B2
Non-planar semiconductor device having doped sub-fin region and method to fabricate same
Tahir Ghani, Portland, OR (US); Salman Latif, Sunnyvale, CA (US); and Chanaka D. Munasinghe, Hillsboro, OR (US)
Assigned to Tahoe Research, Ltd., Dublin (IE)
Filed by Tahoe Research, Ltd., Dublin (IE)
Filed on Mar. 17, 2023, as Appl. No. 18/185,728.
Application 18/185,728 is a continuation of application No. 17/183,214, filed on Feb. 23, 2021, granted, now 11,631,673.
Application 17/183,214 is a continuation of application No. 16/812,726, filed on Mar. 9, 2020, granted, now 10,964,697, issued on Mar. 30, 2021.
Application 16/812,726 is a continuation of application No. 16/510,688, filed on Jul. 12, 2019, granted, now 10,622,359, issued on Apr. 14, 2020.
Application 16/510,688 is a continuation of application No. 16/103,430, filed on Aug. 14, 2018, granted, now 10,396,079, issued on Aug. 27, 2019.
Application 16/103,430 is a continuation of application No. 14/779,936, granted, now 10,056,380, issued on Aug. 21, 2018, previously published as PCT/US2013/046902, filed on Jun. 20, 2013.
Prior Publication US 2023/0223406 A1, Jul. 13, 2023
Int. Cl. H01L 27/092 (2006.01); H01L 21/225 (2006.01); H01L 21/265 (2006.01); H01L 21/3105 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 27/088 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01)
CPC H01L 27/0924 (2013.01) [H01L 21/2255 (2013.01); H01L 21/26513 (2013.01); H01L 21/31051 (2013.01); H01L 21/823431 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 27/0886 (2013.01); H01L 29/0847 (2013.01); H01L 29/66803 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a first fin of a first semiconductor material, the first fin having a lower fin portion and an upper fin portion;
a first dielectric layer comprising a first dielectric material, the first dielectric layer along sidewalls of the lower fin portion of the first fin but not along sidewalls of the upper fin portion of the first fin;
a first insulating layer comprising a second dielectric material different from the first dielectric material, the first insulating layer over the first dielectric layer;
a dielectric fill material over the first insulating layer, wherein a portion of the upper fin portion of the first fin extends above a top surface of the dielectric fill material; and
a gate electrode, wherein the gate electrode is over a top of the first fin and the dielectric fill material and laterally adjacent to sidewalls of the upper fin portion of the first fin.