US 12,191,301 B2
Integrated circuit
Ya-Qi Ma, Shanghai (CN); Lei Pan, Shanghai (CN); and Zhen Tang, Shanghai (CN)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW); and TSMC CHINA COMPANY LIMITED, Shanghai (CN)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW); and TSMC CHINA COMPANY LIMITED, Shanghai (CN)
Filed on Jun. 29, 2022, as Appl. No. 17/853,698.
Application 17/853,698 is a continuation of application No. 16/807,003, filed on Mar. 2, 2020, granted, now 11,380,671.
Claims priority of application No. 202010078071.9 (CN), filed on Feb. 2, 2020.
Prior Publication US 2022/0336442 A1, Oct. 20, 2022
Int. Cl. H01L 27/02 (2006.01); H01L 27/06 (2006.01)
CPC H01L 27/0266 (2013.01) [H01L 27/0292 (2013.01); H01L 27/0617 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a first transistor coupled between a pad and a first voltage terminal that provides a first supply voltage;
a second transistor coupled in parallel with the first transistor, wherein a breakdown voltage of the first transistor is different from a trigger voltage of the second transistor; and
a resistive device coupled between the pad and a second voltage terminal that provides a second supply voltage higher than the first supply voltage,
wherein the resistive device is configured to operate with the second supply voltage in an electrostatic discharge (ESD) event when the first and second transistors are configured to discharge a ESD current between the pad and the first voltage terminal.