US 12,191,300 B2
Integrated circuit structure with resistive semiconductor material for back well
Robert J. Gauthier, Jr., Williston, VT (US); Rajendran Krishnasamy, Essex Junction, VT (US); Anupam Dutta, Bangalore (IN); Anindya Nath, Essex Junction, VT (US); Xiangxiang Lu, Essex Junction, VT (US); Satyasuresh Vvss Choppalli, Bangalore (IN); and Lin Lin, Houston, TX (US)
Assigned to GlobalFoundries U.S. Inc., Malta, NY (US)
Filed by GlobalFoundries U.S. Inc., Malta, NY (US)
Filed on May 11, 2022, as Appl. No. 17/662,921.
Prior Publication US 2023/0369314 A1, Nov. 16, 2023
Int. Cl. H01L 27/02 (2006.01)
CPC H01L 27/0262 (2013.01) [H01L 27/0266 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) structure comprising:
a semiconductor substrate having a deep well;
a device within a first portion of the deep well, the device including:
a first doped semiconductor material coupled to a first contact;
a second doped semiconductor material coupled to a second contact, wherein the deep well couples the first doped semiconductor material to the second doped semiconductor material;
a first back well within a second portion of the deep well; and
a first resistive semiconductor material within the deep well and interposed between the first portion of the deep well and the second portion of the deep well.