	US 12,191,296 B2
	Method of producing a multi-chip assembly
Ling Ma, Redondo Beach, CA (US); Robert Haase, San Pedro, CA (US); and Timothy Henson, Mount Shasta, CA (US)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Nov. 8, 2021, as Appl. No. 17/520,924.
Prior Publication US 2023/0145931 A1, May 11, 2023
Int. Cl. H01L 25/00 (2006.01); H01L 21/784 (2006.01); H01L 23/00 (2006.01); H01L 25/07 (2006.01)

CPC H01L 25/50 (2013.01) [H01L 24/24 (2013.01); H01L 24/96 (2013.01); H01L 25/072 (2013.01); H01L 21/784 (2013.01); H01L 2224/24137 (2013.01); H01L 2224/245 (2013.01); H01L 2224/95001 (2013.01); H01L 2224/96 (2013.01); H01L 2924/10156 (2013.01); H01L 2924/10161 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01)]

12 Claims

1. A method of producing multi-chip assemblies, the method comprising:

processing a semiconductor wafer into a plurality of separated dies, the plurality of separated dies including a first group of separated dies and a second group of separated dies; and

via wafer-level processing:

reversing an orientation of the second group of separated dies such that the second group of separated dies have an opposite orientation as the first group of separated dies;

securing the separated dies of the first group and the second group to one another with a dielectric material;

electrically interconnecting groups of two or more adjacent ones of the separated dies from the first group and the second group; and

removing the dielectric material in a region between the groups of electrically interconnected dies to laterally separate the groups of electrically interconnected dies from one another.