	US 12,191,295 B1
	Heterogeneous integration of radio frequency transistor chiplets having interconnections to host wafer circuits for optimizing operating conditions
James F. Buckwalter, Santa Barbara, CA (US); Florian Herrault, Agoura Hills, CA (US); Justin Kim, Santa Barbara, CA (US); Michael Hodge, Huntersville, NC (US); and Daniel S. Green, McLean, VA (US)
Assigned to PseudolithIC, Inc., Santa Barbara, CA (US)
Filed by PseudolithIC, Inc., Santa Barbara, CA (US)
Filed on Jun. 25, 2024, as Appl. No. 18/754,058.
Int. Cl. H01L 25/18 (2023.01); H01L 29/737 (2006.01); H01L 29/778 (2006.01); H03K 17/56 (2006.01)

CPC H01L 25/18 (2013.01) [H01L 29/737 (2013.01); H01L 29/7786 (2013.01); H03K 17/56 (2013.01)]

24 Claims

1. An electronic assembly for heterogeneous integration of radio frequency (RF) transistor chiplets having interconnections to host wafer circuits, the assembly comprising:

at least one RF transistor chiplet each having a chiplet circuit including a high-electron-mobility transistor (HEMT) or a heterojunction bipolar transistor (HBT);

a host wafer having at least one host wafer circuit for the purpose of producing bias conditions that optimize performance of the HEMT or HBT, the at least one host wafer circuit including one of:

first circuitry to provide a DC bias of the HEMT or HBT; or

second circuitry configured to sense radio-frequency operating conditions of the HEMT or HBT; and

electrical interconnects between the chiplet and the host wafer, wherein the electrical interconnects electrically connect the host wafer circuit to the chiplet circuit.