	US 12,191,267 B2
	Nanowire bonding interconnect for fine-pitch microelectronics
Belgacem Haba, Saratoga, CA (US); and Ilyas Mohammed, Santa Clara, CA (US)
Assigned to Adeia Semiconductor Technologies, LLC, San Jose, CA (US)
Filed by ADEIA SEMICONDUCTOR TECHNOLOGIES LLC, San Jose, CA (US)
Filed on Jul. 11, 2022, as Appl. No. 17/811,713.
Application 17/811,713 is a division of application No. 16/776,182, filed on Jan. 29, 2020, granted, now 11,387,202, issued on Jul. 12, 2022.
Claims priority of provisional application 62/812,778, filed on Mar. 1, 2019.
Prior Publication US 2023/0105341 A1, Apr. 6, 2023
Int. Cl. H01L 23/00 (2006.01)

CPC H01L 24/05 (2013.01) [H01L 24/03 (2013.01); H01L 24/08 (2013.01); H01L 24/29 (2013.01); H01L 24/80 (2013.01); H01L 24/83 (2013.01); H01L 2221/1094 (2013.01); H01L 2224/0311 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05639 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05655 (2013.01); H01L 2224/05684 (2013.01); H01L 2224/0807 (2013.01); H01L 2224/08503 (2013.01); H01L 2224/29027 (2013.01); H01L 2224/29028 (2013.01); H01L 2224/80815 (2013.01); H01L 2224/83895 (2013.01)]

20 Claims

1. A method, comprising:

creating a nanoporous layer on a conductive pad of a microelectronic device or wafer;

creating nanowires within pores of the nanoporous layer;

removing or recessing at least part of the nanoporous layer to reveal at least a part of the nanowires for at least conductive contact with an opposing conductive surface of an opposing microelectronic device or wafer; and

direct hybrid bonding a bonding surface of the microelectronic device or wafer to the opposing microelectronic device or wafer, wherein the direct hybrid bonding comprises direct metal bonding the nanowires to the opposing conductive surface and direct bonding the nanoporous layer to the opposing microelectronic device or wafer.