CPC H01L 24/05 (2013.01) [H01L 24/03 (2013.01); H01L 29/42304 (2013.01); H01L 29/42376 (2013.01); H01L 2224/03614 (2013.01); H01L 2224/03622 (2013.01); H01L 2224/05017 (2013.01); H01L 2224/05018 (2013.01); H01L 2224/05076 (2013.01); H01L 2224/05082 (2013.01); H01L 2224/05083 (2013.01); H01L 2224/05084 (2013.01); H01L 2224/05088 (2013.01); H01L 2224/05138 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05181 (2013.01); H01L 2224/05184 (2013.01); H01L 2224/05186 (2013.01); H01L 2224/05324 (2013.01); H01L 2224/05338 (2013.01); H01L 2224/05344 (2013.01); H01L 2224/05347 (2013.01); H01L 2224/05366 (2013.01); H01L 2224/05384 (2013.01); H01L 2224/05557 (2013.01); H01L 2224/05564 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01)] | 20 Claims |
1. A semiconductor device comprising:
a semiconductor substrate;
a first layer formed of an oxide film provided on an upper surface of the semiconductor substrate;
a second layer which is a layer formed on an upper surface of the first layer and at least selectively having a projection and a recess in an upper surface of the second layer, the projection and the recess being deeper than unintentional fine bumps on an upper surface of the second layer, the unintentional fine bumps occurring during manufacturing process for forming the upper surface of the second layer in a planar shape;
a barrier metal formed on the upper surface of the second layer according to a shape of the projection and the recess; and
a pad in close contact with the second layer via the barrier metal.
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