US 12,191,264 B2
Thermal performance improvement and stress reduction in semiconductor device modules
Yong Liu, Cumberland Foreside, ME (US); and Qing Yang, Shenzhen (CN)
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed by SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Phoenix, AZ (US)
Filed on Apr. 6, 2022, as Appl. No. 17/658,118.
Prior Publication US 2023/0326876 A1, Oct. 12, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/373 (2006.01); H01L 25/00 (2006.01); H01L 25/07 (2006.01); H01L 25/18 (2023.01)
CPC H01L 23/562 (2013.01) [H01L 21/4807 (2013.01); H01L 21/565 (2013.01); H01L 23/3735 (2013.01); H01L 24/40 (2013.01); H01L 24/48 (2013.01); H01L 25/072 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2224/40225 (2013.01); H01L 2224/48225 (2013.01); H01L 2924/1203 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/15787 (2013.01); H01L 2924/351 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device module comprising:
a substrate including:
a first ceramic layer; and
a first metal layer disposed on a first surface of the substrate; and
a first semiconductor die, a first side of the first semiconductor die being coupled to the first metal layer;
a second semiconductor die, a first side of the second semiconductor die being coupled to the first metal layer; and
a signal distribution assembly including a second metal layer, the second metal layer having:
a first side, the first side being planar; and
a second side opposite the first side, the second side being non-planar and including:
a base portion;
a first post extending from the base portion, the first post being coupled with a second side of the first semiconductor die opposite the first side of the first semiconductor die; and
a second post extending from the base portion, the second post being coupled with a second side of the second semiconductor die opposite the first side of the second semiconductor die, the signal distribution assembly electrically coupling the first semiconductor die with the second semiconductor die.