	US 12,191,254 B2
	Electronic devices including tiered stacks including conductive structures isolated by slot structures, and related systems and methods
Sidhartha Gupta, Boise, ID (US); and Anilkumar Chandolu, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 1, 2021, as Appl. No. 17/453,041.
Prior Publication US 2023/0139457 A1, May 4, 2023
Int. Cl. H01L 23/528 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); G11C 16/04 (2006.01)

CPC H01L 23/5283 (2013.01) [H01L 21/76837 (2013.01); H01L 23/53257 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); G11C 16/0483 (2013.01)]

25 Claims

1. An electronic device, comprising:

a stack comprising tiers of alternating conductive structures and insulative structures overlying a source tier;

strings of memory cells extending vertically through the stack, the strings of memory cells individually comprising a channel material extending vertically through the stack;

an additional stack overlying the stack and comprising tiers of alternating additional conductive structures and additional insulative structures;

pillars extending through the additional stack and overlying the strings of memory cells, each of the pillars horizontally offset in a first horizontal direction and in a second horizontal direction transverse to the first horizontal direction from a center of a corresponding string of memory cells;

conductive lines overlying the pillars; and

interconnect structures directly contacting the pillars and the conductive lines.