	US 12,191,250 B2
	Method of forming bottom electrode via for memory device
Zhen Yu Guan, Changhua County (TW); Sheng-Wen Fu, Hsinchu (TW); and Hsun-Chung Kuang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 21, 2022, as Appl. No. 17/725,906.
Claims priority of provisional application 63/303,801, filed on Jan. 27, 2022.
Prior Publication US 2023/0238318 A1, Jul. 27, 2023
Int. Cl. H01L 23/522 (2006.01); G11C 11/16 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H10N 50/01 (2023.01); H10N 50/10 (2023.01); H10N 50/80 (2023.01)

CPC H01L 23/5226 (2013.01) [G11C 11/161 (2013.01); H01L 21/76831 (2013.01); H01L 23/528 (2013.01); H10N 50/01 (2023.02); H10N 50/10 (2023.02); H10N 50/80 (2023.02)]

20 Claims

1. A method of forming an integrated chip structure, comprising:

forming a lower insulating structure over a lower dielectric structure surrounding one or more lower interconnects;

patterning the lower insulating structure to form a bottom electrode via opening exposing the one or more lower interconnects;

forming a barrier layer within the bottom electrode via opening and over the lower insulating structure;

forming a conductive core material over the barrier layer;

performing a mechanical polishing process to remove a first part of the conductive core material;

performing a buffing process to remove a second part of the conductive core material and to form a conductive core;

forming a bottom electrode layer onto the conductive core and the barrier layer;

forming a data storage layer onto the bottom electrode layer; and

forming a top electrode layer onto the data storage layer.