US 12,191,248 B2
Semiconductor arrangement and method of making
Wan-Yu Lo, Zhongli (TW); Chung-Hsing Wang, Baoshan Township (TW); Chin-Shen Lin, Taipei (TW); Kuo-Nan Yang, Hsinchu (TW); Hsiang-Ku Shen, Hsinchu (TW); and Dian-Hau Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED, Hsin-Chu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED, Hsin-Chu (TW)
Filed on Jun. 1, 2021, as Appl. No. 17/335,242.
Claims priority of provisional application 63/157,394, filed on Mar. 5, 2021.
Prior Publication US 2022/0285263 A1, Sep. 8, 2022
Int. Cl. H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 49/02 (2006.01)
CPC H01L 23/5223 (2013.01) [H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 28/40 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor arrangement, comprising:
a first conductive plate;
a first portion of a dielectric material over the first conductive plate;
a second conductive plate over the first portion of the dielectric material;
a second portion of the dielectric material over the second conductive plate;
a third conductive plate over the second portion of the dielectric material;
a third portion of the dielectric material over the third conductive plate;
a fourth conductive plate over the third portion of the dielectric material;
a fourth portion of the dielectric material over the fourth conductive plate;
a fifth conductive plate over the fourth portion of the dielectric material;
a first conductive via directly physically contacting the first conductive plate and the fifth conductive plate;
a second conductive via directly physically contacting the third conductive plate; and
a third conductive via directly physically contacting the second conductive plate and the fourth conductive plate.
 
7. A semiconductor arrangement, comprising:
a first voltage domain connected to at least one of a core region or a logic region configured to operate at a first supply voltage, the first voltage domain comprising:
a first supply terminal for receiving the first supply voltage from a first voltage source;
a first reference terminal; and
a first capacitor network connected across the first supply terminal and the first reference terminal and comprising a stack of alternating layers of a conductive material having a first thickness and a dielectric material having a second thickness, wherein the first supply voltage is less than a breakdown voltage of the dielectric material having the second thickness; and
a second voltage domain connected to an input/output region configured to operate at a second supply voltage different than the first supply voltage, the second voltage domain comprising:
a second supply terminal for receiving the second supply voltage from a second voltage source;
a second reference terminal; and
a second capacitor network connected across the second supply terminal and the second reference terminal and comprising the stack of alternating layers of the conductive material having the first thickness and the dielectric material having the second thickness, wherein the second supply voltage is greater than the breakdown voltage of the dielectric material having the second thickness.
 
15. A semiconductor arrangement, comprising:
a first voltage domain connected to at least one of a core region or a logic region configured to operate at a first supply voltage, the first voltage domain comprising:
a first capacitor;
a second capacitor connected in parallel with the first capacitor;
a first supply terminal for receiving the first supply voltage from a first voltage source;
a first reference terminal, wherein the first capacitor and the second capacitor are connected in parallel with the first supply terminal and the first reference terminal;
a second voltage domain connected to an input/output region configured to operate at a second supply voltage different than the first supply voltage, the second voltage domain comprising:
a third capacitor;
a fourth capacitor connected in series with the third capacitor;
a second supply terminal for receiving the second supply voltage; and
a second reference terminal connected to the third capacitor.