CPC H01L 23/49816 (2013.01) [H01L 23/3171 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 24/05 (2013.01); H01L 24/16 (2013.01); H01L 25/18 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16147 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/16238 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01)] | 20 Claims |
1. A semiconductor package comprising:
an interposer substrate having a first region comprising a plurality of through-vias, a second region adjacent to a periphery of the first region and spaced apart from an edge of the interposer substrate, and a third region disposed between the second region and the edge of the interposer substrate;
a passivation layer on a first surface of the interposer substrate in the first region and the second region;
a plurality of dummy patterns on the first surface of the interposer substrate in at least one of the first region and the second region, and embedded in the passivation layer;
first and second semiconductor chips on a second surface of the interposer substrate opposite to the first surface; and
an underfill resin in contact with at least a portion of the first surface of the interposer substrate in the third region, and at least a portion of the edge of the interposer substrate between the first surface and the second surface.
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