US 12,191,235 B2
Integrated cooling assemblies including signal redistribution and methods of manufacturing the same
Belgacem Haba, Saratoga, CA (US); and Rajesh Katkar, Milpitas, CA (US)
Assigned to Adeia Semiconductor Bonding Technologies Inc., San Jose, CA (US)
Filed by Adeia Semiconductor Bonding Technologies Inc., San Jose, CA (US)
Filed on Nov. 17, 2023, as Appl. No. 18/512,567.
Claims priority of provisional application 63/467,307, filed on May 17, 2023.
Prior Publication US 2024/0387324 A1, Nov. 21, 2024
Int. Cl. H01L 23/473 (2006.01); H01L 23/00 (2006.01); H01L 23/427 (2006.01); H01L 23/498 (2006.01); H01L 25/18 (2023.01); H10B 80/00 (2023.01)
CPC H01L 23/473 (2013.01) [H01L 23/427 (2013.01); H01L 23/49822 (2013.01); H01L 24/08 (2013.01); H01L 25/18 (2013.01); H10B 80/00 (2023.02); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/08221 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device package comprising:
a semiconductor device having an active side and a backside opposite the active side; and
a plurality of bonded layers, comprising:
a first layer and a second layer, the first layer having a recessed surface, a support feature that extends downwardly from the recessed surface to the second layer, and sidewalls that extend downwardly from the recessed surface to the second layer and surround the recessed surface and the support feature; and
a first interconnect vertically disposed through the support feature, wherein the first interconnect is electrically coupled to the semiconductor device through direct hybrid bonds formed between the second layer and the semiconductor device.