US 12,191,212 B2
Semiconductor method and device
Yi-Cheng Li, Yunlin (TW); Pin-Ju Liang, Hsinchu (TW); Ta-Chun Ma, New Taipei (TW); Pei-Ren Jeng, Chu-Bei (TW); and Yee-Chia Yeo, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 5, 2022, as Appl. No. 17/737,766.
Claims priority of provisional application 63/219,890, filed on Jul. 9, 2021.
Prior Publication US 2023/0019633 A1, Jan. 19, 2023
Int. Cl. H01L 21/8238 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 27/092 (2006.01)
CPC H01L 21/823878 (2013.01) [H01L 21/02532 (2013.01); H01L 21/30604 (2013.01); H01L 21/823821 (2013.01); H01L 27/0924 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a fin extending from a substrate;
depositing a liner over a top surface and sidewalls of the fin, wherein a minimum thickness of the liner is selected according to a first germanium concentration of the fin;
forming a shallow trench isolation (STI) region adjacent the fin, wherein the fin comprises a first portion above a topmost surface of the STI region, and a second portion below the topmost surface of the STI region, wherein the first portion comprises silicon germanium and the second portion comprises silicon;
removing a first portion of the liner on the sidewalls of the fin, the first portion of the liner being above the topmost surface of the STI region; and
forming a gate stack on sidewalls and a top surface of the fin, wherein the gate stack is in physical contact with the liner.