	US 12,191,210 B2
	Formation of high density 3D circuits with enhanced 3D conductivity
H. Jim Fulford, Albany, NY (US); Mark I. Gardner, Albany, NY (US); and Partha Mukhopadhyay, Albany, NY (US)
Assigned to Tokyo Electron Limited, Tokyo (JP)
Filed by Tokyo Electron Limited, Tokyo (JP)
Filed on Apr. 14, 2022, as Appl. No. 17/721,124.
Claims priority of provisional application 63/188,039, filed on May 13, 2021.
Prior Publication US 2022/0367290 A1, Nov. 17, 2022
Int. Cl. H01L 21/8238 (2006.01); H01L 21/8234 (2006.01); H01L 27/092 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01)

CPC H01L 21/823814 (2013.01) [H01L 21/823418 (2013.01); H01L 21/823487 (2013.01); H01L 21/823885 (2013.01); H01L 27/092 (2013.01); H01L 29/456 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01); H01L 29/78642 (2013.01)]

10 Claims

1. A method of microfabrication, the method comprising:

forming a layer stack, the layer stack including a plurality of layers of a metal, each of the plurality of layers of the metal separated by a layer of a dielectric;

forming an opening in the layer stack such that a semiconductor layer beneath the plurality of layers of the metal is uncovered;

forming a vertical channel structure within the opening by epitaxial growth, the vertical channel structure having an interface of a silicide metal with a first metal layer of the plurality of metal layers, the interface corresponding to one of a source or a drain connection of a transistor; and

annealing the silicide metal above a temperature threshold to form a silicide interface between the vertical channel structure and the first metal layer.