US 12,191,208 B2
Dual strained semiconductor substrate and patterning
Kangguo Cheng, Schenectady, NY (US); Shogo Mochizuki, Mechanicville, NY (US); and Juntao Li, Cohoes, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Sep. 23, 2021, as Appl. No. 17/482,573.
Prior Publication US 2023/0086888 A1, Mar. 23, 2023
Int. Cl. H01L 27/12 (2006.01); H01L 21/8238 (2006.01); H01L 21/84 (2006.01); H01L 27/092 (2006.01)
CPC H01L 21/823807 (2013.01) [H01L 21/84 (2013.01); H01L 27/092 (2013.01); H01L 27/1203 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A semiconductor structure comprising:
a dielectric layer on top of a first semiconductor stack, wherein the first semiconductor stack is compressively strained, and wherein the first semiconductor stack comprises Silicon Germanium (SiGe); and
a second semiconductor stack on top of the dielectric layer, wherein the second semiconductor stack is tensely strained.