US 12,191,205 B2
Semiconductor device and manufacturing method thereof
Minghwei Hong, Hsinchu County (TW); Juei-Nai Kwo, Hsinchu County (TW); Tun-Wen Pi, Hsinchu County (TW); Hsien-Wen Wan, Kaohsiung (TW); Yi-Ting Cheng, Kaohsiung (TW); and Yu-Jie Hong, New Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); and NATIONAL TAIWAN UNIVERSITY, Taipei (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); and NATIONAL TAIWAN UNIVERSITY, Taipei (TW)
Filed on Mar. 3, 2022, as Appl. No. 17/685,845.
Claims priority of provisional application 63/220,022, filed on Jul. 9, 2021.
Prior Publication US 2023/0011006 A1, Jan. 12, 2023
Int. Cl. H01L 21/324 (2006.01); H01L 21/82 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 21/823412 (2013.01) [H01L 21/324 (2013.01); H01L 29/0665 (2013.01); H01L 29/1054 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a semiconductive channel layer on a substrate;
forming a dummy gate on the semiconductive channel layer;
forming gate spacers on opposite sides of the dummy gate;
removing the dummy gate to form a gate trench between the gate spacers, resulting in the semiconductive channel layer exposed in the gate trench;
depositing a semiconductive protection layer in the gate trench and on the semiconductive channel layer;
oxidizing a top portion of the semiconductive protection layer to form an oxidation layer over a remaining portion of the semiconductive protection layer;
after oxidizing the top portion of the semiconductive protection layer, annealing the oxidation layer; and
after annealing the oxidation layer, forming a gate structure over the semiconductive protection layer and in the gate trench.