CPC H01L 21/76898 (2013.01) [H01L 21/76804 (2013.01); H01L 21/76846 (2013.01); H01L 21/76871 (2013.01); H01L 23/481 (2013.01); H01L 25/105 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 2225/1041 (2013.01)] | 7 Claims |
1. A semiconductor package, comprising:
a substrate, having a through hole formed therethrough, wherein the through hole has a tapered profile, being wider at a frontside surface of the substrate than at a backside surface of the substrate opposite to the frontside surface;
a first barrier layer extending on the backside surface of the substrate;
a second barrier layer, extending along tapered sidewalls of the through hole and on the frontside surface of the substrate;
a routing via, filling the through hole and separated from the tapered sidewalls of the through hole by at least the second barrier layer;
a first routing pattern, extending over the first barrier layer on the backside surface of the substrate and further extending over the routing via, electrically connected to one end of the routing via, and having a protrusion protruding towards the one end of the routing via in correspondence of the through hole;
a second routing pattern, extending over the second barrier layer on the frontside surface of the substrate, wherein the second routing pattern directly contacts another end of the routing via; and
a semiconductor die, electrically connected to the routing via by the first routing pattern.
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