| CPC H01L 21/76897 (2013.01) [H01L 21/31122 (2013.01); H01L 21/67069 (2013.01); H01L 21/76816 (2013.01); H01L 21/76831 (2013.01)] | 20 Claims |
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1. A method, comprising:
receiving a semiconductor substrate that comprises:
a nitride etch stop layer over a gate electrode;
a metal-based etch stop layer over a source/drain contact region, the source/drain contact region being adjacent to the gate electrode, the gate electrode being to a first side of the source/drain contact region, the metal-based etch stop layer covering a surface of the source/drain contact region over an entire span of the surface between the gate electrode to the first side of the source/drain contact region and another gate electrode adjacent to a second side of the source/drain contact region; and
a dielectric layer overlying the metal-based etch stop layer and the nitride etch stop layer;
patterning, to expose respective surfaces of the metal-based etch stop layer and the nitride etch stop layer, the dielectric layer using a patterned resist layer over the dielectric layer as an etch mask; and
etching the metal-based etch stop layer using a plasma etching process that selectively etches the metal-based etch stop layer until the surface of the source/drain contact region is exposed, at least a portion of the nitride etch stop layer remaining over the gate electrode after the plasma etching process, the plasma etching process comprising exposing the semiconductor substrate to a plasma comprising a corrosive material and a fluorine-based reducing agent, wherein the corrosive material comprises chlorine and the fluorine-based reducing agent comprises fluorocarbon.
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