US 12,191,160 B2
Method for making a semiconductor superlattices with different non-semiconductor thermal stabilities
Keith Doran Weeks, Chandler, AZ (US); Nyles Wynn Cody, Tempe, AZ (US); Marek Hytha, Brookline, MA (US); and Robert J. Mears, Wellesley, MA (US)
Assigned to ATOMERA INCORPORATED, Los Gatos, CA (US)
Filed by Atomera Incorporated, Los Gatos, CA (US)
Filed on Jul. 1, 2021, as Appl. No. 17/305,192.
Claims priority of provisional application 63/047,365, filed on Jul. 2, 2020.
Prior Publication US 2022/0005706 A1, Jan. 6, 2022
Int. Cl. H01L 21/00 (2006.01); H01L 21/02 (2006.01); H01L 21/322 (2006.01)
CPC H01L 21/3225 (2013.01) [H01L 21/02507 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method for making a semiconductor device comprising:
forming first and second superlattices adjacent a semiconductor layer and each comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, the second superlattice having a greater thermal stability with respect to thermally induced migration of non-semiconductor atoms from positions within the second superlattice than thermally induced migration of non-semiconductor atoms from positions within the first superlattice; and
heating the first and second superlattices to cause non-semiconductor atoms from the first superlattice to migrate toward the at least one non-semiconductor monolayer of the second superlattice.