US 12,191,157 B2
Manufacturing method of semiconductor memory device
Seung Cheol Lee, Icheon-si (KR); Dae Min Kim, Icheon-si (KR); Dae Sung Kim, Icheon-si (KR); Sang Seob Lee, Icheon-si (KR); and Hyun Woo Jin, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Mar. 3, 2022, as Appl. No. 17/685,611.
Claims priority of application No. 10-2021-0143991 (KR), filed on Oct. 26, 2021.
Prior Publication US 2023/0129758 A1, Apr. 27, 2023
Int. Cl. H01L 21/311 (2006.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01); H10B 41/35 (2023.01); H10B 41/41 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01)
CPC H01L 21/31116 (2013.01) [H10B 41/27 (2023.02); H10B 43/27 (2023.02); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] 11 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor memory device, the method comprising:
alternately stacking sacrificial layers and interlayer insulating layers over a lower structure;
forming a slit passing through the sacrificial layers and the interlayer insulating layers;
removing the sacrificial layers through the slit through a wet etching process; and
removing, through a dry etching process, a byproduct that is produced at ends of the interlayer insulating layers during the wet etching process.