US 12,191,154 B2
Method for manufacturing semiconductor structure, semiconductor structure, and memory
Junbo Pan, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Sep. 27, 2021, as Appl. No. 17/486,707.
Application 17/486,707 is a continuation of application No. PCT/CN2021/108909, filed on Jul. 28, 2021.
Claims priority of application No. 202110791904.0 (CN), filed on Jul. 13, 2021.
Prior Publication US 2023/0013786 A1, Jan. 19, 2023
Int. Cl. H01L 21/308 (2006.01); H01L 21/027 (2006.01)
CPC H01L 21/3086 (2013.01) [H01L 21/0274 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor structure, comprising:
providing a substrate, and forming a stabilizing layer on the substrate;
forming a stabilizing structure consisting of a plurality of linear structures and grooves among the linear structures on the stabilizing layer;
forming a hard mask layer covering the stabilizing structure;
forming a mask pattern connected to a top of the linear structures and an inner wall of the grooves on the hard mask layer;
transferring the mask pattern to the substrate; and
removing the mask pattern and the stabilizing structure; and,
wherein forming the mask pattern connected to the top of the linear structures and the inner wall of the grooves on the hard mask layer comprises:
etching the hard mask layer to form a plurality of hard mask layer strips, wherein thehard mask layer strips are arranged at intervals to form the mask pattern; wherein a preset included angle is formed between a length direction of the hard mask layer strips and a length direction of the linear structures.