US 12,190,995 B2
Memory device and memory system including the same
Byunghoon Jeong, Hwaseong-si (KR); Kyungtae Kang, Seoul (KR); Jangwoo Lee, Seoul (KR); and Jeongdon Ihm, Seongnam-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Aug. 25, 2023, as Appl. No. 18/455,904.
Application 18/455,904 is a continuation of application No. 18/069,685, filed on Dec. 21, 2022, granted, now 11,769,537.
Application 18/069,685 is a continuation of application No. 17/411,421, filed on Aug. 25, 2021, granted, now 11,562,780, issued on Jan. 24, 2023.
Application 17/411,421 is a continuation in part of application No. 17/001,941, filed on Aug. 25, 2020, granted, now 11,107,512, issued on Aug. 31, 2021.
Claims priority of application No. 10-2019-0123349 (KR), filed on Oct. 4, 2019.
Prior Publication US 2023/0402076 A1, Dec. 14, 2023
Int. Cl. G11C 7/22 (2006.01); G11C 7/10 (2006.01); G11C 8/18 (2006.01); G11C 29/42 (2006.01); H03K 19/173 (2006.01)
CPC G11C 7/222 (2013.01) [G11C 7/1057 (2013.01); G11C 7/1063 (2013.01); G11C 7/1084 (2013.01); G11C 8/18 (2013.01); G11C 29/42 (2013.01); H03K 19/1737 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory controller configured to communicate with a memory device through a plurality of lines including a plurality of data lines, the memory controller comprising:
an enable signal generator configured to generate a read enable signal and transmit the read enable signal to the memory device through one of the plurality of lines; and
a first-in first-out (FIFO) circuit configured to store, in response to the read enable signal, status data received from the memory device through at least one of the plurality of data lines in a first period, and to read data received through the plurality of data lines in a second period subsequent to the first period,
wherein the memory controller is configured to determine whether to retrain the memory device based on the status data stored in the FIFO circuit.