US 12,190,990 B2
Deferred fractional memory row activation
James E. Harris, Tyler, TX (US); Thomas Vogelsang, Mountain View, CA (US); Frederick A. Ware, Los Altos Hills, CA (US); and Ian P. Shaeffer, Los Gatos, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Sep. 26, 2023, as Appl. No. 18/373,162.
Application 18/373,162 is a continuation of application No. 17/665,760, filed on Feb. 7, 2022, granted, now 11,804,250.
Application 17/665,760 is a continuation of application No. 17/065,278, filed on Oct. 7, 2020, granted, now 11,270,741, issued on Mar. 8, 2022.
Application 17/065,278 is a continuation of application No. 16/528,523, filed on Jul. 31, 2019, granted, now 10,811,062, issued on Oct. 20, 2020.
Application 16/528,523 is a continuation of application No. 15/889,191, filed on Feb. 5, 2018, granted, now 10,388,337, issued on Aug. 20, 2019.
Application 15/889,191 is a continuation of application No. 15/390,674, filed on Dec. 26, 2016, granted, now 9,911,468, issued on Mar. 6, 2018.
Application 15/390,674 is a continuation of application No. 15/138,424, filed on Apr. 26, 2016, granted, now 9,570,126, issued on Feb. 14, 2017.
Application 15/138,424 is a continuation of application No. 13/640,084, granted, now 9,330,735, issued on May 3, 2016, previously published as PCT/US2012/041758, filed on Jun. 8, 2012.
Claims priority of provisional application 61/512,133, filed on Jul. 27, 2011.
Prior Publication US 2024/0062788 A1, Feb. 22, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/00 (2006.01); G11C 5/02 (2006.01); G11C 7/06 (2006.01); G11C 7/08 (2006.01); G11C 7/10 (2006.01); G11C 7/12 (2006.01); G11C 7/22 (2006.01); G11C 8/08 (2006.01); G11C 8/10 (2006.01); G11C 11/4076 (2006.01); G11C 11/408 (2006.01); G11C 11/4091 (2006.01)
CPC G11C 7/1039 (2013.01) [G11C 5/025 (2013.01); G11C 7/06 (2013.01); G11C 7/065 (2013.01); G11C 7/08 (2013.01); G11C 7/12 (2013.01); G11C 7/222 (2013.01); G11C 8/08 (2013.01); G11C 8/10 (2013.01); G11C 11/4076 (2013.01); G11C 11/4087 (2013.01); G11C 11/4091 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of operation within a memory control component, the method comprising:
outputting a first command/address value to a dynamic random access memory (DRAM) component during a first interval, the first command/address value including a row address and a row command, the row command instructing the DRAM component to activate a first global word line that (i) is specified by the row address and (ii) corresponds to a first row of DRAM cells within the DRAM component; and
outputting a second command/address value to the DRAM component during a second interval, the second command/address value including a first sub-row address, a first column address and a first column command, the first column command instructing the DRAM component to activate a first sub-row word line that (i) is specified by the first sub-row address, (ii) corresponds to a first sub-row of DRAM cells within the first row of DRAM cells, and (iii) enables conduction, when activated, of contents of the first sub-row of DRAM cells to a first sub-row region of a sense amplifier bank within the DRAM component.