US 12,190,989 B2
Data output buffer and semiconductor apparatus including the same
Kyu Dong Hwang, Icheon-si (KR); Bo Ram Kim, Icheon-si (KR); and Dae Han Kwon, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jun. 13, 2023, as Appl. No. 18/334,261.
Application 18/334,261 is a division of application No. 17/361,018, filed on Jun. 28, 2021, granted, now 11,699,467.
Claims priority of application No. 10-2021-0037586 (KR), filed on Mar. 23, 2021.
Prior Publication US 2023/0326496 A1, Oct. 12, 2023
Int. Cl. G11C 7/00 (2006.01); G11C 7/10 (2006.01); H03K 19/00 (2006.01); H03K 19/017 (2006.01)
CPC G11C 7/1039 (2013.01) [G11C 7/1057 (2013.01); G11C 7/1096 (2013.01); H03K 19/0005 (2013.01); H03K 19/01742 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A data output buffer comprising:
a first driver configured to directly receive an impedance calibration code, drive a data input/output (I/O) pad according to an input signal and allow data drivability to be controlled according to the impedance calibration code;
a second driver configured to directly receive emphasis signals, perform a de-emphasis operation on the data I/O pad and allow de-emphasis drivability to be controlled according to a selection code and the emphasis signals; and
a selection circuit configured to output one of a fixing code and the impedance calibration code as the selection code according to a selection signal,
wherein the first driver and the second driver are coupled to the data I/O pad directly.