US 12,190,985 B2
Sense amplifier circuit, memory device, and operation method thereof
Kanyu Cao, Hefei (CN); and Weibing Shang, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on May 11, 2022, as Appl. No. 17/741,722.
Application 17/741,722 is a continuation of application No. PCT/CN2020/074385, filed on Feb. 6, 2020.
Prior Publication US 2022/0270653 A1, Aug. 25, 2022
Int. Cl. G11C 7/06 (2006.01); G11C 7/08 (2006.01); G11C 7/12 (2006.01)
CPC G11C 7/062 (2013.01) [G11C 7/08 (2013.01); G11C 7/12 (2013.01)] 49 Claims
OG exemplary drawing
 
1. A sense amplifier circuit, comprising:
an amplification circuit, comprising:
a first inverting amplifier and a second inverting amplifier, wherein an input of the first inverting amplifier is connected to an output of the second inverting amplifier at a first node, and an input of the second inverting amplifier is connected to an output of the first inverting amplifier at a second node, wherein the first inverting amplifier comprises a first transistor and a second transistor, a gate terminal of the first transistor and a gate terminal of the second transistor are directly connected together to form the input of the first inverting amplifier at the first node; the second inverting amplifier comprises a third transistor and a fourth transistor, and a gate terminal of the third transistor and a gate terminal of the fourth transistor are directly connected together to form the input of the second inverting amplifier at the second node; and
a compensation circuit coupled to the amplification circuit and configured to:
in an equalization stage, control a first bitline to connect to the first node and the second node, and control a second bitline to connect to the first node and the second node; and
in an offset compensation stage, switch off a connection between the first bitline and the second node, and switch off a connection between the second bitline and the first node, at least remain on a connection between the first bitline and the first node or remain on a connection between the second bitline and the second node.