US 12,190,982 B2
Memory and operation method thereof
Seung Chan Kim, Gyeonggi-do (KR); and Keon Ho Lee, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Jan. 26, 2022, as Appl. No. 17/585,156.
Claims priority of application No. 10-2021-0130108 (KR), filed on Sep. 30, 2021.
Prior Publication US 2023/0101173 A1, Mar. 30, 2023
Int. Cl. G11C 7/10 (2006.01); G11C 7/20 (2006.01); G11C 29/00 (2006.01); G11C 29/18 (2006.01); G11C 29/44 (2006.01)
CPC G11C 29/76 (2013.01) [G11C 7/106 (2013.01); G11C 7/1087 (2013.01); G11C 7/20 (2013.01); G11C 29/18 (2013.01); G11C 29/4401 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A memory comprising:
first to Nth register circuits each configured to receive and store a failure address transferred from a memory controller when a corresponding selection signal of first to Nth selection signals is activated, where N is an integer equal to or greater than 2;
first to Nth resource latch circuits configured to store first to Nth resource signals indicating availability of the first to Nth register circuits, respectively; and
a priority selection circuit configured to activate, when two or more of the first to Nth resource signals are activated, a high priority selection signal of selection signals respectively corresponding to the activated resource signals among the first to Nth selection signals,
wherein the high priority selection signal activates one register circuit having a high priority among the first to Nth register circuits.