US 12,190,973 B2
Memory device performing sensing operation and method of operating the same
Se Chun Park, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on May 31, 2023, as Appl. No. 18/325,999.
Claims priority of application No. 10-2022-0166108 (KR), filed on Dec. 1, 2022.
Prior Publication US 2024/0185939 A1, Jun. 6, 2024
Int. Cl. G11C 29/12 (2006.01); G11C 11/4099 (2006.01); G11C 16/34 (2006.01); G11C 29/02 (2006.01); G11C 29/50 (2006.01); G11C 29/52 (2006.01)
CPC G11C 29/12005 (2013.01) [G11C 11/4099 (2013.01); G11C 16/34 (2013.01); G11C 29/021 (2013.01); G11C 29/025 (2013.01); G11C 29/50 (2013.01); G11C 29/50004 (2013.01); G11C 29/52 (2013.01); G11C 2029/1204 (2013.01); G11C 2207/063 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A memory device comprising:
a plurality of memory cells;
a defect detector configured to generate defect information indicating a defect state in which a value of a cell current measured in a sensing operation on selected memory cells among the plurality of memory cells is less than a threshold value; and
a test controller configured to:
count fail bits from a result of a test operation performed on the selected memory cells using a test reference current in response to the defect information, and
set a bit line voltage to be used in the sensing operation based on a comparison result between a number of fail bits detected in the test operation and a reference number.