US 12,190,969 B2
Plane level dedicated starting program voltage to reduce program time for multi-plane concurrent program operation
Ke Zhang, Shanghai (CN); and Liang Li, Shanghai (CN)
Assigned to SanDisk Technologies LLC, Addison, TX (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Aug. 25, 2022, as Appl. No. 17/895,625.
Prior Publication US 2024/0071525 A1, Feb. 29, 2024
Int. Cl. G11C 16/06 (2006.01); G11C 16/10 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/10 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory apparatus, comprising:
memory cells connected to one of a plurality of word lines and disposed in memory holes and configured to retain a threshold voltage corresponding to one of a plurality of data states, the memory holes organized in rows grouped in a plurality of strings, the plurality of strings comprise a plurality of blocks comprising a plurality of planes; and
a control means coupled to the plurality of word lines and the memory holes and configured to:
program the memory cells connected to one of the plurality of word lines and associated with one of the plurality of strings in each of the plurality of planes and acquire a smart verify programming voltage individually for each of the plurality of planes in a smart verify operation including a plurality of smart verify loops, and
concurrently program at least some of the memory cells connected to each of the plurality of word lines in each of the plurality of planes in a program operation using the smart verify programming voltage individually acquired for each of the plurality of planes in the smart verify operation.