US 12,190,968 B2
Memory circuit, system and method for rapid retrieval of data sets
Eli Harari, Saratoga, CA (US)
Assigned to SUNRISE MEMORY CORPORATION, San Jose, CA (US)
Filed by SUNRISE MEMORY CORPORATION, San Jose, CA (US)
Filed on Jan. 23, 2024, as Appl. No. 18/420,073.
Application 17/394,733 is a division of application No. 16/744,067, filed on Jan. 15, 2020, granted, now 11,120,884, issued on Sep. 14, 2021.
Application 16/107,306 is a division of application No. 15/248,420, filed on Aug. 26, 2016, granted, now 10,121,553, issued on Nov. 6, 2018.
Application 16/894,596 is a division of application No. 16/107,118, filed on Aug. 21, 2018, granted, now 10,748,629, issued on Aug. 18, 2020.
Application 16/107,118 is a division of application No. 15/248,420, filed on Aug. 26, 2016, granted, now 10,121,553, issued on Nov. 6, 2018.
Application 18/420,073 is a continuation of application No. 17/978,144, filed on Oct. 31, 2022, granted, now 11,915,768.
Application 17/978,144 is a continuation of application No. 17/394,733, filed on Aug. 5, 2021, granted, now 11,488,676, issued on Nov. 1, 2022.
Application 16/744,067 is a continuation in part of application No. 16/582,996, filed on Sep. 25, 2019, granted, now 10,971,239, issued on Apr. 6, 2021.
Application 16/582,996 is a continuation of application No. 16/107,306, filed on Aug. 21, 2018, granted, now 10,622,078, issued on Apr. 14, 2020.
Application 15/248,420 is a continuation in part of application No. 15/220,375, filed on Jul. 26, 2016, granted, now 9,892,800, issued on Feb. 13, 2018.
Application 17/978,144 is a continuation of application No. 16/894,596, filed on Jun. 5, 2020, granted, now 11,508,445, issued on Nov. 22, 2022.
Claims priority of provisional application 62/363,189, filed on Jul. 15, 2016.
Claims priority of provisional application 62/260,137, filed on Nov. 25, 2015.
Claims priority of provisional application 62/235,322, filed on Sep. 30, 2015.
Prior Publication US 2024/0161837 A1, May 16, 2024
Int. Cl. G11C 16/34 (2006.01); G06F 17/16 (2006.01); G06N 3/063 (2023.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); H01L 21/28 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01L 29/792 (2006.01); H01L 29/92 (2006.01); H10B 43/27 (2023.01); H10B 43/10 (2023.01)
CPC G11C 16/3431 (2013.01) [G06F 17/16 (2013.01); G06N 3/063 (2013.01); G11C 11/5628 (2013.01); G11C 11/5635 (2013.01); G11C 11/5642 (2013.01); G11C 16/0416 (2013.01); G11C 16/0466 (2013.01); G11C 16/0483 (2013.01); G11C 16/0491 (2013.01); G11C 16/10 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H01L 29/40117 (2019.08); H01L 29/66833 (2013.01); H01L 29/78633 (2013.01); H01L 29/7926 (2013.01); H01L 29/92 (2013.01); H10B 43/27 (2023.02); H10B 43/10 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A 3-dimensional array of NOR memory strings formed above a planar surface of a semiconductor substrate, wherein each NOR memory string comprises:
a first group of thin-film memory transistors; and
a second group of thin-film memory transistors, wherein the thin-film memory transistors in the first group and the thin-film memory transistors in the second group share a common drain region and a common source region, wherein the thin-film memory transistors in the first group are configured to be accessed within a first access time and the thin-film memory transistors in the second group are configured to be accessed within a second access time, and wherein the first access time is less than the second access time.