US 12,190,966 B2
Memory system and processing method of memory system
Tomoya Sanuki, Yokkaichi Mie (JP); Hitomi Tanaka, Tokyo (JP); Tatsuro Hitomi, Yokohama Kanagawa (JP); Yasuhito Yoshimizu, Kawasaki Kanagawa (JP); Masayuki Miura, Tokyo (JP); and Yoshihiro Ohba, Kawasaki Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Aug. 30, 2022, as Appl. No. 17/899,447.
Claims priority of application No. 2022-031020 (JP), filed on Mar. 1, 2022.
Prior Publication US 2023/0282289 A1, Sep. 7, 2023
Int. Cl. G11C 16/26 (2006.01); G11C 16/04 (2006.01); G11C 16/34 (2006.01); H10B 43/00 (2023.01)
CPC G11C 16/26 (2013.01) [G11C 16/0483 (2013.01); G11C 16/34 (2013.01); G11C 16/3431 (2013.01); H10B 43/00 (2023.02)] 12 Claims
OG exemplary drawing
 
1. A method of processing a memory system that includes a substrate with a connector and a semiconductor memory chip connected to the connector, the method comprising:
detaching the semiconductor memory chip from the connector;
performing an annealing process with respect to the semiconductor memory chip detached from the connector; and
after the annealing process, attaching the semiconductor memory chip to the connector on the substrate.