US 12,190,965 B2
Coding to decrease error rate discrepancy between pages
Curtis Egan, Brighton, CO (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 24, 2022, as Appl. No. 17/894,398.
Prior Publication US 2024/0071518 A1, Feb. 29, 2024
Int. Cl. G11C 16/26 (2006.01); G11C 11/56 (2006.01)
CPC G11C 16/26 (2013.01) [G11C 11/5642 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A method, comprising:
identifying, after a duration, voltage drifts of a plurality of read voltages, the plurality of read voltages corresponding to a plurality of voltage levels between adjacent voltage threshold regions of a memory cell at a memory device;
mapping the plurality of read voltages to one of a plurality of pages of the memory cell using a unit-distance code, wherein the plurality of pages are associated with respective subsets of the plurality of read voltages according to the unit-distance code;
identifying a plurality of average read voltage drifts each corresponding to one of the plurality of pages based at least in part on the voltage drifts of read voltages within the respective subsets of the plurality of read voltages; and
operating the memory device using the unit-distance code based at least in part on a range of the plurality of average read voltage drifts each corresponding to one of the plurality of pages associated with the unit-distance code being less than one or more other ranges of a plurality of average read voltage drifts that each correspond to one of the plurality of pages associated with one or more other unit-distance codes.