| CPC G11C 16/26 (2013.01) [G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01)] | 20 Claims |
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1. A method of operating a nonvolatile memory device that includes at least one memory block including a plurality of cell strings where each of the plurality of cell strings includes a string selection transistor, a plurality of memory cells and a ground selection transistor which are connected in series and disposed in a vertical direction between a bit-line and a common source line, the method comprising:
during a word-line setup period, setting up each of a plurality of word-lines coupled to the plurality of memory cells to a respective target level;
during a sensing period, performing a sensing operation on target memory cells of the plurality of memory cells by applying a read voltage to a selected word-line coupled to the target memory cells, among the plurality of word-lines while applying a read pass voltage to unselected word-lines among the plurality of word-lines;
during a word-line recovery period, performing a word-line recovery operation by recovering a voltage level of the read pass voltage applied to the unselected word-lines to a level of an internal voltage; and
during a discharge period within the word-line recovery period, consuming the internal voltage connected to the unselected word-lines by activating a particular circuit of the nonvolatile memory device,
wherein the particular circuit is supplied with the internal voltage and is not associated with the word-line recovery operation.
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