US 12,190,963 B2
Methods of operating memory devices based on sub-block positions and related memory system
Se-Hwan Park, Suwon-si (KR); and Wan-Dong Kim, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Aug. 19, 2023, as Appl. No. 18/235,838.
Application 16/840,290 is a division of application No. 16/004,770, filed on Jun. 11, 2018, granted, now 10,614,891, issued on Apr. 7, 2020.
Application 18/235,838 is a continuation of application No. 17/525,934, filed on Nov. 14, 2021, granted, now 11,804,268.
Application 17/525,934 is a continuation of application No. 17/010,681, filed on Sep. 2, 2020, granted, now 11,232,841, issued on Jan. 25, 2022.
Application 17/010,681 is a continuation in part of application No. 16/840,290, filed on Apr. 3, 2020, granted, now 10,971,235, issued on Apr. 6, 2021.
Claims priority of application No. 10-2017-0113343 (KR), filed on Sep. 5, 2017.
Prior Publication US 2023/0395158 A1, Dec. 7, 2023
Int. Cl. G11C 11/34 (2006.01); G06F 13/16 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01); G11C 16/14 (2006.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01)
CPC G11C 16/24 (2013.01) [G06F 13/1668 (2013.01); G11C 11/5628 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/3418 (2013.01); G06F 2213/0024 (2013.01); G11C 16/14 (2013.01); G11C 2211/5648 (2013.01); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a plurality of three-dimensional structures including a first structure and a second structure, each of the plurality of three-dimensional structures including:
a plurality of NAND strings that include a first NAND string and a second NAND string, each of the plurality of NAND strings including:
a plurality of memory cells that include a plurality of first memory cells and a plurality of second memory cells, and
a plurality of sub-blocks that include a first sub-block and a second sub-block;
a first channel disposed in the first sub-block;
a second channel disposed in the second sub-block; and
a control logic configured to program the plurality of first memory cells on the first NAND string in a first sub-block of the first structure in a first order, and to program the plurality of second memory cells on the second NAND string in a second sub-block of the second structure in a second order that is different from the first order, wherein:
the plurality of first memory cells of each of the plurality of NAND strings are disposed in the first sub-block of each of the plurality of three-dimensional structures,
the first sub-block of the first structure is disposed at the same vertical level as a first sub-block of the second structure,
a horizontal width of an upper portion of the first channel is greater than a horizontal width of a lower portion of the first channel,
a horizontal width of an upper portion of the second channel is greater than a horizontal width of a lower portion of the second channel,
the first channel and the second channel are connected to each other and configured to form one channel of each of the plurality of NAND strings,
the upper portion of the second channel is connected to the lower portion of the first channel at a particular vertical level, and
at the particular vertical level, the horizontal width of the upper portion of the second channel is greater than the horizontal width of the lower portion of the first channel.