| CPC G11C 16/14 (2013.01) [G11C 16/26 (2013.01)] | 20 Claims |
|
1. A storage device comprising:
a first non-volatile memory device;
a second non-volatile memory device;
a third non-volatile memory device; and
a storage controller including processing circuitry configured to
set first to third read level offsets of the respective first to third non-volatile memory devices by,
extracting a respective one of first through third on-cell count values by performing a respective one of first through third soft erase operations on the respective one of the first to third non-volatile memory devices, and
determining a respective one of the first to third read level offsets based on a distribution of the respective one of the first through third on-cell count values determined through the respective one of the first through third soft erase operations,
select first to third defense code parameter sets each corresponding to the respective first to third read level offsets, and
transmit first to third read commands to the respective first to third non-volatile memory devices based on the selected respective first to third defense code parameter sets such that the first to third read commands include the respective one of the first to third read level offsets.
|