US 12,190,957 B2
Dynamic step voltage level adjustment
Carmine Miccoli, Boise, ID (US); and Andrew Bicksler, Nampa, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 7, 2022, as Appl. No. 17/939,273.
Claims priority of provisional application 63/274,776, filed on Nov. 2, 2021.
Prior Publication US 2023/0133227 A1, May 4, 2023
Int. Cl. G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/12 (2006.01); G11C 16/24 (2006.01); G11C 16/32 (2006.01)
CPC G11C 16/12 (2013.01) [G11C 16/08 (2013.01); G11C 16/102 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); G11C 16/32 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array comprising a set of memory cells; and
processing logic, operatively coupled with the memory array, to perform operations comprising:
receiving a request to execute a programming operation on the set of memory cells;
causing a first set of programming pulses corresponding to a first step voltage level to be applied to one or more wordlines associated with the set of memory cells;
determining that a programming voltage level associated with a programming pulse of the first set of programming pulses satisfies a condition, wherein the condition is satisfied when the programming voltage level is greater than or equal to a programming voltage threshold level; and
causing a second set of programming pulses corresponding to a second step voltage level to be applied to the one or more wordlines associated with the set of memory cells in response to the condition being satisfied.