| CPC G11C 16/08 (2013.01) [G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/16 (2013.01); G11C 16/30 (2013.01); G11C 16/32 (2013.01); G11C 16/3427 (2013.01); G11C 16/24 (2013.01); H10B 69/00 (2023.02)] | 20 Claims |
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1. A semiconductor memory device, comprising:
a conductive region having a surface extending in a first direction and a second direction intersecting the first direction;
a first line connected to the conductive region;
a first select gate line stacked above the conductive region in a third direction orthogonal to the first direction and the second direction;
a plurality of word lines stacked above the first select gate line in the third direction;
a second select gate line stacked above the word lines in the third direction;
a plurality of bit lines disposed above the second select gate line in the third direction and extending in the first direction;
a memory cell array including a plurality of memory strings extending in the third direction and connected between corresponding bit lines and the first line, each of the memory strings including
a first select transistor having a gate to which the first select gate line is connected,
memory cell transistors each having a gate to which a respective one of the word lines is connected, and
a second select transistor having a gate to which the second select gate line is connected;
a first voltage apply circuit configured to apply a voltage to the first line; and
a row decoder configured to apply voltages to the first select gate line, the word lines, and the second select gate line, respectively, wherein
before writing data to a part of the memory cell transistors having the gates connected to a selected word line among the word lines:
the row decoder is controlled to:
at a first timing,
apply a first voltage to the first select gate line, and
apply a second voltage to the selected word line, and to a non-selected word line disposed in a layer between the selected word line and the conductive region, to turn on the first select transistor and the memory cell transistors connected to the selected word line and the non-selected word line;
at a second timing after the first timing, apply a third voltage lower than the first voltage to the first select gate line to turn off the first select gate transistor;
at a third timing after the second timing, apply a fourth voltage higher than the third voltage to the selected word line and the non-selected word line; and
at a fourth timing after the third timing, apply a fifth voltage higher than the fourth voltage to the selected word line, and
the first voltage apply circuit is controlled to:
at a fifth timing that is simultaneous with or after the first timing and before the second timing, apply a sixth voltage to the first line; and
at a sixth timing after the second timing and before the third timing, apply a seventh voltage lower than the sixth voltage to the first line.
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