US 12,190,952 B2
Semiconductor memory device and method of manufacturing the semiconductor memory device
Minami Tanaka, Yokkaichi (JP); and Naoyuki Iida, Yokkaichi (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Feb. 9, 2022, as Appl. No. 17/650,422.
Claims priority of application No. 2021-152067 (JP), filed on Sep. 17, 2021.
Prior Publication US 2023/0092799 A1, Mar. 23, 2023
Int. Cl. G11C 16/04 (2006.01); H01L 23/528 (2006.01); H01L 27/11519 (2017.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01)
CPC G11C 16/0483 (2013.01) [H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] 18 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a plurality of interconnect layers stacked above a substrate and spaced apart from each other in a first direction;
a memory pillar configured to penetrate the plurality of interconnect layers in the first direction;
a first member and a second member each having a longitudinal direction set to a second direction intersecting the first direction when viewed from a top, the first member and the second member being arranged in the second direction and penetrating the plurality of interconnect layers in the first direction; and
a dividing portion provided between the first member and the second member,
wherein the dividing portion includes a plurality of insulating layers spaced apart from each other in the first direction,
the plurality of insulating layers each include a first portion and a second portion,
the first portion is provided between the first member and the second portion,
the second portion is provided between the first portion and the second member, and
the first portion and the second portion each have an individual arc shape when viewed from the top and are in contact with each other.