US 12,190,947 B2
Imprint recovery for memory arrays
Jonathan J. Strand, Boise, ID (US); Sukneet Singh Basuta, Meridian, ID (US); Shashank Bangalore Lakshman, Boise, ID (US); and Jonathan D. Harms, Meridian, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 27, 2021, as Appl. No. 17/562,598.
Application 17/562,598 is a continuation of application No. 16/581,005, filed on Sep. 24, 2019, granted, now 11,217,303.
Prior Publication US 2022/0199155 A1, Jun. 23, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/56 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01); G11C 29/50 (2006.01)
CPC G11C 11/5628 (2013.01) [G11C 11/5642 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/3427 (2013.01); G11C 29/50004 (2013.01); G11C 29/50016 (2013.01); G11C 2029/5004 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A memory system, comprising:
one or more memory arrays comprising a set of memory cells; and
circuitry coupled with the one or more memory arrays and configured to cause the memory system to:
receive a command to perform an imprint recovery procedure configured to alleviate a predisposition of the set of memory cells toward storing respective first logic states over respective second logic states;
initiate the imprint recovery procedure based at least in part on receiving the command;
transmit an indication of a status of the imprint recovery procedure based at least in part on initiating the imprint recovery procedure;
receive an indication to pause the imprint recovery procedure after initiating the imprint recovery procedure;
pause the imprint recovery procedure based at least in part on receiving the indication; and
resume the imprint recovery procedure after pausing the imprint recovery procedure.