a transistor having a gate terminal coupled to a word-line, a source terminal couple to a bit-line, and a drain terminal coupled to a storage node;

a plurality of capacitors having a first terminal coupled to the storage node, wherein a second terminal of an individual capacitor of the plurality of capacitors is coupled to an individual plate-line; and

one or more circuitries to perform a first read operation during a first phase on a selected capacitor of the plurality of capacitors, wherein the one or more circuitries is to perform a second read operation during a second phase, wherein the second read operation mitigates read disturb effects on unselected capacitors of the plurality of capacitors, wherein the one or more circuitries is to ramp a voltage on a plate-line coupled to the selected capacitor in a staircase fashion to a supply voltage level during the first phase, wherein the one or more circuitries is to perform a writeback operation after the second read operation, and wherein the writeback operation and the second read operation are separated by one or more cycles where the word-line, the bit-line, and the individual plate-line are pulled to ground.