CPC G11C 11/4091 (2013.01) | 16 Claims |
1. A memory cell comprising:
a write transistor; and
a read transistor coupled to the write transistor, the write transistor and the read transistor coupled at a storage node, the storage node being for storing data;
wherein, at least one among the write transistor and the read transistor includes a threshold voltage adjusting layer, and a threshold voltage of the write transistor and/or the read transistor is adjustable, and the storage node is connected to a control terminal of the read transistor.
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