US 12,190,941 B2
Memory cell and memory device thereof
Po-Hao Tseng, Taichung (TW); and Feng-Min Lee, Hsinchu (TW)
Assigned to MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed by MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed on Dec. 28, 2022, as Appl. No. 18/147,015.
Prior Publication US 2024/0221822 A1, Jul. 4, 2024
Int. Cl. G11C 11/4091 (2006.01)
CPC G11C 11/4091 (2013.01) 16 Claims
OG exemplary drawing
 
1. A memory cell comprising:
a write transistor; and
a read transistor coupled to the write transistor, the write transistor and the read transistor coupled at a storage node, the storage node being for storing data;
wherein, at least one among the write transistor and the read transistor includes a threshold voltage adjusting layer, and a threshold voltage of the write transistor and/or the read transistor is adjustable, and the storage node is connected to a control terminal of the read transistor.