a subword driver block comprising:

at least first and second active regions extending in a first direction; and

one or more common diffusion regions spaced in the first direction and configured to merge the first and second active regions;

a gate electrode layer comprising:

first gate electrode extending in a second direction substantially perpendicularly to the first direction, the first gate electrode overlaid across the first and second active regions in a plan view to form first and second transistors; and

second gate electrode extending in the second direction, the second gate electrode overlaid across the first and second active regions in the plan view to form third and fourth transistors;

a diffusion contact overlaid on the first active region, the diffusion contact is shared by the second and fourth transistors via a respective common diffusion region of the one or more common diffusion regions;

a wiring layer comprising a plurality of interconnections extending in the second direction and coupled to respective word lines of a memory cell array; and

a contact wiring coupled to the diffusion contact, wherein the contact wiring is positioned between first and second interconnections of the plurality of interconnections.