| CPC G11C 11/4085 (2013.01) [G11C 11/4087 (2013.01)] | 20 Claims |
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1. A memory device comprising:
a memory cell array having a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines;
a row decoder circuit connected to the plurality of word lines, and configured to select a first word line among the plurality of word lines based on a row address;
an active counter circuit configured to generate a control signal based on comparing a number of accesses to the first word line with a preset threshold value;
a three-phase word line controller configured to determine an operation mode of the sub word line driver circuit based on the control signal; and
a sub word line driver circuit configured to:
in a row-hammer protection mode, apply a selected operating voltage to the first word line, and apply a first unselected operating voltage to a second word line among the plurality of word lines, which is different from the first word line; and
in a normal mode, apply the selected operating voltage to the first word line, and apply a second unselected operating voltage to the second word line, wherein the second unselected operating voltage has a voltage level that is lower than the first unselected operating voltage.
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