US 12,190,935 B2
Memory and operation method thereof
Sang Woo Yoon, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Nov. 3, 2022, as Appl. No. 17/980,141.
Claims priority of application No. 10-2022-0063514 (KR), filed on May 24, 2022.
Prior Publication US 2023/0384942 A1, Nov. 30, 2023
Int. Cl. G11C 11/406 (2006.01); G06F 3/06 (2006.01); G11C 11/4078 (2006.01); G11C 11/408 (2006.01); G11C 11/4091 (2006.01); G11C 11/4094 (2006.01); G11C 29/12 (2006.01)
CPC G11C 11/40615 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0653 (2013.01); G06F 3/0673 (2013.01); G11C 11/40603 (2013.01); G11C 11/40611 (2013.01); G11C 11/4078 (2013.01); G11C 11/408 (2013.01); G11C 11/4087 (2013.01); G11C 11/4091 (2013.01); G11C 11/4094 (2013.01); G11C 29/1201 (2013.01); G11C 2029/1204 (2013.01)] 12 Claims
OG exemplary drawing
 
1. An operation method of a memory, the operation method comprising:
receiving an active command and an active address;
determining whether a row corresponding to the active address and a row corresponding to a target row address share a bit line sense amplifier;
activating the row corresponding to the active address; and
activating the row corresponding to the target row address when the row corresponding to the active address and the row corresponding to the target row address are determined to share the bit line sense amplifier.