| CPC G11C 11/40615 (2013.01) [G11C 11/4076 (2013.01)] | 9 Claims |
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1. A memory comprising:
a memory core;
a list storage circuit suitable for storing a weak row list that includes a list of rows that have been determined to be more vulnerable to a row hammer attack and data loss, as compared to other rows in the memory core also row hammered attacked, wherein the rows more vulnerable to the row hammer attack are divided into multiple levels according to a degree of vulnerability; and
a row hammer attack detection circuit suitable for selecting rows that are row-hammer-attacked among rows in the memory core as hammered rows,
wherein the row hammer attack detection circuit increases a probability that the rows in the list of rows that have been determined to be more vulnerable to a row hammer attack and data loss in the list storage circuit are selected as the hammered rows.
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