US 12,190,932 B2
Memory device, memory controller, and methods thereof
Tony Schenk, Dresden (DE)
Assigned to Ferroelectric Memory GmbH, Dresden (DE)
Filed by Ferroelectric Memory GmbH, Dresden (DE)
Filed on Jun. 13, 2022, as Appl. No. 17/806,673.
Prior Publication US 2023/0402083 A1, Dec. 14, 2023
Int. Cl. G11C 11/22 (2006.01)
CPC G11C 11/2273 (2013.01) [G11C 11/221 (2013.01); G11C 11/2259 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory controller configured to cause a destructive read operation to determine an initial memory state of a memory element, the memory element comprising at least one remanent polarizable portion, the destructive read operation comprising:
causing an alternating sequence of voltage drops of opposite polarities over the at least one remanent polarizable portion of the memory element; and, subsequently,
determining the initial memory state of the memory element based on an electrical behavior of the memory element caused by the alternating sequence of voltage drops.