| CPC G11C 11/223 (2013.01) [G11C 11/2273 (2013.01); G11C 11/2275 (2013.01)] | 20 Claims |
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1. A structure comprising:
a multiplexing circuit including: multiple data line inputs; multiple select line inputs; and a multiplexing circuit output node; and
multiple memory cells, wherein each memory cell includes:
a first transistor;
a second transistor, wherein the second transistor has an electric field-based programmable threshold voltage and wherein the first transistor and the second transistor are connected in series between a first voltage source line and a second voltage source line;
a sense node at a junction between the first transistor and the second transistor;
a memory cell output node;
a first inverter; and
a second inverter, wherein the first inverter and the second inverter are connected in series between the sense node and the memory cell output node and wherein the memory cell output node is connected to one of the data line inputs of the multiplexing circuit.
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