a first array composed of a plurality of sampling latches configured to latch n-bit image data for each channel;

a second array composed of a plurality of holding latches configured to latch the image data latched in the sampling latches at a latch timing determined for each of a plurality of latch groups;

a signal generating circuit configured to generate a plurality of latch enable signal corresponding to the plurality of latch groups and apply each of the plurality of latch enable signals to the holding latches correspond of the plurality of latch groups so that holding latches included in different latch groups operate at different timings to latch image data latched in the sampling latches as different latch timing; and

a third array composed of level shifters configured to shift a voltage level of the image data output from the holding latches,

wherein each of the latch groups is composed of holding latches.